This application claims priority to Korean Patent Application No. 2005-55698, filed on Jun. 27, 2005 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to operational amplifiers, and more particularly, to an operational amplifier having a pseudo-differential output stage for operating with low voltage.
2. Description of the Related Art
With advancement of fabrication technology, integrated circuits with reduced line widths operate with lower voltages. For example, an integrated circuit with a line width of about 90 nm operates with a voltage of about 1 volt. However, the integrated circuit may not operate properly with such a low voltage, especially when the integrate circuit is comprised of field effect transistors that should operate in saturation.
FIG. 1 is a block diagram of a conventional two-stage operational amplifier with multiple stages for obtaining a high DC gain. For obtaining the high DC gain, a folded-cascode amplifier A1 is used as a first stage, and for obtaining a wide output range, a common source amplifier A2 is used as a second stage.
In the prior art operational amplifier of FIG. 1, the two stages A1 and A2 each are differential amplifiers. FIG. 2 is a circuit diagram of such a folded-cascode amplifier A1 and such a common source amplifier A2 of FIG. 1. The folded-cascode amplifier A1 comprises differential input NMOSFETs (N-channel metal oxide semiconductor field effect transistors) M1 and M2 with a biasing NMOSFET M3 having a bias BS1 applied thereon.
In addition, the folded-cascode amplifier A1 includes a cascode load comprised of NMOSFETs M5, M6, M7, M8, M9, M10, M11, and M12 having biases BS2, BS3, BS4, and CMFB1 applied thereon. The bias CMFB1 is a common-mode feed-back bias that determines a common-mode voltage level of the first and second amplified signals OUT+ and OUT−. A feed-back circuit (not shown in FIG. 2) is used for controlling the common-mode voltage of the first and second amplified signals OUT+ and OUT− with the common-mode feed-back bias CMFB1.
The gates of the NMOSFETs M1 and M2 have differential input signals IN+ and IN− applied thereon. The folded-cascode amplifier A1 generates a first amplified signal OUT− at the drains of M8 and M10 and generates a second amplified signal OUT+ at the drains of M7 and M9. The difference of OUT+ and OUT− is an amplification of a difference between IN+ and IN−.
The common source amplifier A2 includes differential input field effect transistors M15 and M16 having gates with the first and second amplified signals OUT+ and OUT− respectively applied thereon. Field effect transistors M13 and M14 form loads for the differential input field effect transistors M15 and M16. A first re-amplified signal is formed at the drains of M14 and M16, and a second re-amplified signal is formed at the drains of M13 and M15. The difference between such first and second re-amplified signals generated by the common source amplifier A2 is an amplification of the difference between the first and second amplified signals from the folded-cascode amplifier A1.
The common source amplifier A2 also includes a biasing field effect transistor M17 having a bias CMFB2 applied thereon. The bias CMFB2 is a common-mode feed-back bias that determines a common-mode voltage level of the first and second re-amplified signals generated by the common source amplifier A2. A feed-back circuit (not shown in FIG. 2) is used for controlling the common-mode voltage level of such first and second re-amplified signals with the common-mode feed-back bias CMFB2.
For proper operation of the operational amplifier in FIG. 2, all of the transistors should operate in saturation with the following Expression 1 being satisfied:Vdd−Vss>4*V_DSsat +V_th  [Expression 1]
Vdd is the voltage of a high power source, and Vss is the voltage of a low power source. V_DSsat is a minimum drain-to-source voltage for operating a transistor in saturation. V_th is a threshold voltage of a transistor.
When the operational amplifier has a line width of about 90 nm, Vdd−Vss is about 1.0 volt. However, 4*V_DSsat +V_th may be larger than 1.0 volt. For example, V_th may be about 0.3 volts, and V_DSsat may be about 0.2 volts such that 4*V_DSsat +V_th is about 1.1 volts.
An output common-mode voltage level of the first stage A1 should be equal to that of an input common-mode voltage level of the second stage A2. For example, when the output common-mode voltage of the first stage A1 is set at about a half of Vdd−Vss (0.5 volts), a minimum of 2*V_DSsat +V_th that is desired for the input common-mode voltage level of the second stage A2 is 0.5 volts. Due to a body effect in the input transistors M15 and M16, the threshold voltage V—th for M15 and M16 is increased to about 0.4 volts such that M17 cannot reach saturation.
For preventing such a problem, the input common-mode voltage level of the second stage A2 may be set higher to 0.5 volts. However, the output common-mode voltage of the first stage A1 is then increased such that a voltage margin for operating the output transistors M7 and M8 in saturation is decreased. When Vdd−Vss is about 0.9 volts, such transistors M7 and M8 cannot reach saturation.
When the transistors in the operational amplifier of FIG. 2 are not in saturation, the DC gain is decreased or the transconductance varies. In that case, the operational amplifier may not satisfy performance requirements.
FIG. 3A shows a simulation graph of transient responses of the conventional operational amplifier when the power voltage Vdd−Vss is at 1.0 volt or 0.9 volts. Referring to FIG. 3A, the operational amplifier settles to a lower voltage level for the lower power voltage. FIG. 3B is a partially enlarged view of a portion of FIG. 3A. Referring to FIG. 3B, when the power voltage Vdd−Vss is 1.0 volt, a settling time of the output voltage of the operational amplifier is 1.5 ns (nano-seconds), and when the power voltage decreases to 0.9 volts, the settling time of the operational amplifier is increased to 2.7 ns. Thus, the performance of the conventional operational amplifier is degraded when the power voltage is lower.
Thus, an operational amplifier with the field effect transistors operating in saturation even with variation of the power voltage is desired.